Looked through your patch set on GitHub – overall it looks great!
The NVMe CMB patch (#2 in your series) does some math to ensure only
a 2MiB-aligned buffer is registered – with
that in place, could we still enforce 2MiB alignment then in the vtophys notify code path
(#1 in your series)?
No. The check in the NVMe code is for the alignment of the virtual address. However we
cannot guarantee the physical address 2MB alignment lines up with the virtual address 2MB
alignment (mmap cannot assure this condition). So we have to drop that paddr check in the
vtophys notify code for PCI mapped memory.