On Fri, 29 Jan 2021 16:24:25 -0800
Ben Widawsky <ben.widawsky(a)intel.com> wrote:
From: Dan Williams <dan.j.williams(a)intel.com>
The CXL.mem protocol allows a device to act as a provider of "System
RAM" and/or "Persistent Memory" that is fully coherent as if the memory
was attached to the typical CPU memory controller.
With the CXL-2.0 specification a PCI endpoint can implement a "Type-3"
device interface and give the operating system control over "Host
Managed Device Memory". See section 2.3 Type 3 CXL Device.
The memory range exported by the device may optionally be described by
the platform firmware memory map, or by infrastructure like LIBNVDIMM to
provision persistent memory capacity from one, or more, CXL.mem devices.
A pre-requisite for Linux-managed memory-capacity provisioning is this
cxl_mem driver that can speak the mailbox protocol defined in section
18.104.22.168 Mailbox Registers.
For now just land the initial driver boiler-plate and Documentation/
Cc: Jonathan Corbet <corbet(a)lwn.net>
Signed-off-by: Dan Williams <dan.j.williams(a)intel.com>
Signed-off-by: Ben Widawsky <ben.widawsky(a)intel.com>
One thing below about using defs from generic PCI headers where
they are not CXL specific.
diff --git a/drivers/cxl/pci.h b/drivers/cxl/pci.h
new file mode 100644
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* Copyright(c) 2020 Intel Corporation. All rights reserved. */
+#define PCI_CLASS_MEMORY_CXL 0x050210
+ * See section 8.1 Configuration Space Registers in the CXL 2.0
+ * Specification
+#define PCI_EXT_CAP_ID_DVSEC 0x23
+#define PCI_DVSEC_VENDOR_ID_CXL 0x1E98
+#define PCI_DVSEC_VENDOR_ID_OFFSET 0x4
+#define PCI_DVSEC_ID_CXL 0x0
+#define PCI_DVSEC_ID_OFFSET 0x8
include/uapi/linux/pci-regs.h includes equivalents of generic parts of
this already though PCI_DVSEC_HEADER1 isn't exactly informative naming.
+#define PCI_DVSEC_ID_CXL_REGLOC 0x8
+#endif /* __CXL_PCI_H__ */