As it is tie to PASID this is done using IOMMU so looks for caller
of amd_iommu_bind_pasid() or intel_svm_bind_mm() in GPU the existing
user is the AMD GPU driver see:
Ah thanks. This cleared things up for me. A quick search shows there are still no users of
intel_svm_bind_mm() but I see the AMD version used in that GPU driver.
One thing I could not grok from the code how the GPU driver indicates which DMA events
require ATS translations and which do not. I am assuming the driver implements someway of
indicating that and its not just a global ON or OFF for all DMAs? The reason I ask is that
I looking at if NVMe was to support ATS what would need to be added in the NVMe spec above
and beyond what we have in PCI ATS to support efficient use of ATS (for example would we
need a flag in the submission queue entries to indicate a particular IO's SGL/PRP
should undergo ATS).