回复：技术规划与技术研发
by 晏检
linux-nvdimm: 您好！
技术规划与技术研发高级实务
时间地点：2016年12月16-17日北京 授课讲师：陈小文
学习费用：3600 元/位
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培训对象：技术副总/CTO、研发部经理、预研部经理，技术研究部经理、技术专家、技术骨干、技术经理等
课程信息：
课程背景
本课程深刻剖析华为的技术管理体系，包括技术规划和技术研发的流程和组织及其相关的思想和方法，课程通过理论讲解、案例分析、现场研讨和课堂演练的方式帮助学员理解这套优秀的管理体系，并初步诊断学员所在企业在技术管理方面的不足以帮助这些企业逐步构建起适合自己的技术管理体系。
本课程能够帮助企业缓解甚至解决以下问题：
1）技术项目随意立项，缺乏统一的技术项目规划或规划的项目难以执行，缺乏合适的立项判断依据，往往基于研发人员的意愿或者技术原因，而不是产品和市场/价值的原因，导致技术项目的成果无法发挥应有的价值；
2）产品研发过程中由于某些技术迟迟无法突破而导致产品不能及时推上市场，或者因为技术方案不成熟而导致产品上市后出现较大的质量问题；
3）各个产品相对独立地研发，产品的研发缺乏技术平台和公共组件的支持或平台和组件对产品研发的支持程度较低，产品研发的周期比较长，各个产品之间存在较多的重复研发；
4）技术研发项目或者依照产品研发项目的过程要求，或者没有统一的过程要求，对技术研发项目的管理或者过严，限制技术人员的创意，或者过松，导致项目的效率比较低。
课程收益
1. 学习优秀企业技术研发管理体系的框架、核心思想及其运作特点
2. 学习多种类型技术研发项目的技术规划方法，包括技术预研项目、技术平台/技术组件项目和产品预研项目，着重拓宽技术规划的源头、识别和定义各种类型的技术研发项目、规范技术规划运作、着力建立支持高效产品开发的技术分层体系
3. 学习多种类型技术研发项目的技术开发流程、组织和运作，掌握技术研发项目的特点和规律，提升技术研发的效率
4. 通过案例分析和演练，加深对所学内容的掌握，并“学以致用”
课程内容
第一部分 优秀的技术管理体系 优秀的企业是怎么做技术管理的
讲师观点：
不少人认为，企业的技术能力主要依赖于一些技术“牛人”的存在和发挥。如果单单看具体的技术项目，可能如此。但要持续地提升企业的技术能力，运作良好的技术管理体系则是成功的关键要素，技术“牛人”在这样的管理体系中才能够形成合力，发挥更大的作用。
学习优秀企业的技术管理体系，深刻理解该技术管理体系的方方面面，然后再结合企业自身的技术特点，能够逐渐构建起适合本企业且运作良好的技术管理体系。
1. 技术管理概述
1.1 技术管理的基本概念
1.2 技术管理的内容和目标
1.3 技术管理的核心思想
1.4 技术管理的体系框架
2. 技术规划管理
2.1 技术规划组织
2.2 技术规划流程
2.3 技术规划分析
2.4 技术规划选择
2.5 技术规划设计
2.6 技术规划路标
2.7 技术项目任务书
2.8 技术规划实施
3. 技术研发过程管理
3.1 技术项目类型
3.2 技术研发流程概述
3.3 技术开发流程
3.4 技术预研流程
3.5 产品预研流程
3.6 技术研发的组织和运作机制
第二部分 案例分享：典型企业的技术管理成长之路
讲师观点：
“他山之石，可以攻玉”，借鉴别人的成长之路，探索适合自己的路。
0. 案例企业简介
1. 企业初创阶段
1.1 项目制的组织特点
1.2 项目运作情况介绍
1.3 技术管理的问题分析
2. 技术积累阶段
2.1 承上启下的经验总结
2.2 初级的技术项目规划
2.3 技术项目的粗放管理
3. 企业扩张阶段
3.1 企业的产品扩张
3.2 企业扩张阶段的问题分析
3.3 技术共享的行动和困难
4. 平台积累阶段
4.1 企业的产品平台战略
4.2 产品平台的选择和发展
4.3 产品平台的组织演变
5. 企业发展阶段
5.1 运作良好的组织架构
5.2 技术管理的主要成果
第三部分 研讨和演练：我们在技术管理方面如何才能够变得优秀
讲师观点：
理解优秀，分析差距，探索适合自己的技术管理体系，实现“学以致用”。
1. 差距分析演练
使用差距分析表，结合课程学习的内容和所在企业的技术管理现状，分析出本企业的优秀实践和需要改进的方面。
2. 构建适合自己的技术管理体系
通过该演练检查学员对技术管理体系的理解。
第四部分 课程总结
【讲师介绍】—— 陈小文先生
原华为产品规划与技术规划经理
IPD-CMMI体系专家
产品与技术规划专家
平台与技术开发专家
IPMP项目管理专家
研发流程与质量管理专家
【工作经历及专业背景】
陈小文老师是著名的产品与技术规划专家，从事产品研发和技术开发工作长达15年，在长期的研发管理实践中积累了丰富的产品研发技术和管理经验。
陈小文老师曾就职于华为、大连华信、TCL研究院等知名企业，具有十几年以上产品研发及管理工作经验（含通信、医疗器材、保险、车联网等领域），历任技术经理、研发工程师、项目经理、系统工程师、部门经理、Marketing及产品规划经理、质量经理、产品经理等职位。
近年来，陈小文老师主要从事研发管理的培训与咨询服务，其丰富的产品研发技术与研发管理经验为无数高科技企业提供了大量的实际建议，同时也赢得了客户的高度评价。
【授课风格】
陈小文老师授课比较注重理论与实践的结合，能够通过身边的案例、现实的实例、以深入浅出的方式，讲解复杂的专业知识。课程上以学员对知识的实际掌握情况进行模拟演练，并能够在传授学员知识和技能的同时帮助学员培育自己的思考问题、解决问题的能力。
【擅长领域】
技术管理、技术开发、技术平台、敏捷软件项目管理、产品开发流程、研发项目管理、IPD开发流程、集成产品开发（IPD）、产品规划等。
【核心课程】
《技术规划与技术开发高级实务》、《软件项目管理高级实务》、《软件系统设计高级实务》 、《软件需求管理高级实务》、《敏捷项目管理高级实务》等
【部分咨询及培训客户】
东明机电、无限极、宝钢研究院、锐明科技、百富环球、二十九所、南京液压机电、美的生活电器、美的厨房、麦博电器、江淮汽车技术中心、长安汽车、五菱汽车、上海龙工、东方网信、三一重工、浪潮通信、东方通信、京信通信、元征科技、全志科技、欧普照明、从兴电子、顺洛电子、广电运通、新国都、上海BCD、深圳华普电子、握奇数据、理邦精密仪器、海康威视、科锐光电、创真软件、金蝶软件、亚信科技等。
【部分客户评价摘录】
1、课程不是高深的理论堆砌，而是真正适用企业的实用干货，可以在学习后立刻应用到企业内部的管理中去；
2、实战经验丰富，对企业管理中遇到的各疑难杂症有独特的解决思路和解决经验，学到了很多，也收获很多；
3、讲师的高层管理经验，造就了他的高层视角和贴近企业实际，对工作有很强的指导意义；
4、课程安排合理，理论讲解和案例、练习穿插进行，兴趣盎然。
5、课程内容比较系统全面，陈老师讲的这些方法很实用！
6、课程设置合理，培训较为专业，对提高我们公司产品研发和产品创新流程建设有较大促进！
5 years, 6 months
[PATCH] libnvdimm, pfn: fix align attribute
by Dan Williams
Fix the format specifier so that the attribute can be parsed correctly.
Currently it returns decimal 1000 for a 4096-byte alignment.
Cc: <stable(a)vger.kernel.org>
Reported-by: Dave Jiang <dave.jiang(a)intel.com>
Fixes: 315c562536c4 ("libnvdimm, pfn: add 'align' attribute, default to HPAGE_SIZE")
Signed-off-by: Dan Williams <dan.j.williams(a)intel.com>
---
drivers/nvdimm/pfn_devs.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/nvdimm/pfn_devs.c b/drivers/nvdimm/pfn_devs.c
index cea8350fbc7e..a2ac9e641aa9 100644
--- a/drivers/nvdimm/pfn_devs.c
+++ b/drivers/nvdimm/pfn_devs.c
@@ -108,7 +108,7 @@ static ssize_t align_show(struct device *dev,
{
struct nd_pfn *nd_pfn = to_nd_pfn_safe(dev);
- return sprintf(buf, "%lx\n", nd_pfn->align);
+ return sprintf(buf, "%ld\n", nd_pfn->align);
}
static ssize_t __align_store(struct nd_pfn *nd_pfn, const char *buf)
5 years, 6 months
[ndctl PATCH 0/6] updates for device-dax sub-division support
by Dan Williams
Towards being able to script discovery, allocation, and resizing of
device dax instances, extend the libdaxctl apis for pending 4.10 kernel
updates.
---
Dan Williams (6):
util, sysfs: convert add_dev_fn to return the device
libdaxctl: add daxctl_region_get_{id,size,align} apis
daxctl: add dax region iteration apis
ndctl: add per-context private data
test, daxctl: test dax region apis
daxctl: add daxctl_dev_set_size()
daxctl/lib/libdaxctl-private.h | 4 +
daxctl/lib/libdaxctl.c | 217 ++++++++++++++++++++++++++++++++++------
daxctl/lib/libdaxctl.sym | 18 +++
daxctl/libdaxctl.h | 12 ++
ndctl/lib/libndctl-private.h | 2
ndctl/lib/libndctl.c | 122 ++++++++++------------
ndctl/lib/libndctl.sym | 2
ndctl/libndctl.h.in | 2
test/libndctl.c | 68 ++++++++++++-
util/sysfs.c | 15 +--
util/sysfs.h | 2
11 files changed, 350 insertions(+), 114 deletions(-)
5 years, 6 months
Great CTO Bitcoin Opportunity, Ceramics Engineering, etc.
by Nicholas Meyler
Attention Bitcoin Experts and Other Engineers:
My exciting new client in Los Angles is the first investment bank for digital finance, using bitcoin and blockchain technology, working with the New York Cryptocurrencies Exchange.
For now, they focus on building a crypto-currency trading platform with a focus on ICO (Initial Coin Offering) tokens with smart contracts and in parallel. They are building an investment bank to create a transparent and compliant process for companies to raise funds via ICO. The Group is lead by a successful entrepreneur who recently made a successful exit from his second business with a $100+ million ticket.
CTO Position Summary
The Chief Technology Officer (CTO) is responsible for overseeing all technical aspects of the blockchain and fintech projects. Using an active and practical approach, the CTO will direct all employees in IT and IO departments to attain the company’s strategic goals established in the company’s strategic plan.
Specific responsibilities:
CTO must be able to communicate and collaborate with other departments:
1. CEO, Strategy Board & Product Owner
●Predict and stay ahead of any technical points and issues that might significantly affect the company.
●Advise the CEO and Strategy Board on the long‐term technical, strategic direction of the company and where to, or to not, make large strategic technological bets.
●Provide the CEO and Product Owner with different options on the technical direction of the company and provide sufficient information for deciding what is the best solution to take at any given time.
●Be an ultimate authority for the CEO, Strategy Board, and Product Owner by providing a neutral view which puts the company’s long‐term interests above all else.
2. Engineering/Product development
●Continually improve production pipelines, being involved in the daily execution and engineering team management once the priorities are set.
●Lead development team, assess team performance and help execute recruiting/retention efforts.
●Regular reporting to CEO and Product Owner.
●Continuously optimize across the whole organization to avoid any duplication of effort.
●Ensure alignment of the greater technical organization and, when necessary, arbitrate techno‐centric turf scraps, architecture conflicts, etc.
●Serve as master architect across product lines.
3. Business Development, Partnerships
●Communicate with authority about the market; listen to customer needs; quickly understand their issues, and give good advice on the company’s products to the customers.
●Provide technical due diligence of partner technologies and acquisition targets to make sure they properly fit with the company’s platforms and offerings.
●Keep track of all the tech startups in the same space, and have them stack ranked based on what he/she can glean about their prospects. The CTO should have clear thoughts
about ‐ possible acquisition targets, what expertise is the company missing? Which companies are doing the best work across all of the ancillary areas? Which companies
have the best technical teams? What could competitors buy that would hurt the company? etc.
●Predict if a new technology would have a significant impact on the long‐term technological roadmap for the company.
●Predict long‐term competitive trends due to the constant shifts in the market.
4. Marketing
●Serve as the public face of technology for the company.
●Evangelize the company vision and technical direction through conferences, speaking engagements, and press/media/analyst activities.
●Maintain healthy relationships with designated key industry analysts.
●Support the marketing team in building a large active community around the company’s products (meetups, hackathons, industry conferences, etc.).
●Social engagement marketing through twitter, blog posts, articles/whitepapers, etc.
Education and Experience
●BS in related field and at least seven years’ experience in the Information Technology arena.
●At least two years management and strategic experience in this field or MBA/MS in related field with five years’ experience, 2 of which must be managerial and strategic.
●Electronics Trading Systems/FX.
●Java/Python developer/team lead experience 7+ years.
●Systems Architect skills or background
●Blockchain, Smart contracts, Cryptocurrencies background
●Financial/Blockchain startups background
Additional skills
●Has undergone or overseen technical due diligence of electronic trading platform or similar product
●Strong writing and presentation skills
●Agile master
●Ability to manage remote teams
●Russian language (optional)
Additional requirements
●Location: Los‐Angeles (permanent residence or able to move) preferable, West Coast-based working remotely with weekly flights to Los Angeles ‐ optional
Another new client is one of the world's leading manufacturers of capacitors, seeking a Development Engineer
(2) Senior Development Engineer – Ceramic Dielectric (Spartanburg Area, South Carolina)
This engineer will lead material and process development in the area of ceramic dielectrics for ceramic capacitor products. The candidate should have knowledge and experience with ceramic dielectric formulations, and milling and dispersion of fine ceramic powders. The candidate will be familiar with processing of ceramic powders, dispersants, mixing and milling of micron and sub-micron size powders, formulating multi-component compositions, ceramic thick films and coatings, and electronic properties of ceramics. The candidate will be expected to quickly learn the key aspects of the Company manufacturing technology and process. This person will play a critical role in developing new products using leading edge technologies and will execute experimental work with a minimum of supervision.
Requirements:
A strong technical background and experience are required in Ceramic Science and Engineering, processing with ceramic powders and/or coatings, Design of Experiments, and problem solving. Good communication skills both verbal and written are essential. Experience with material characterization techniques, and electrical property measurements would be preferred, especially with respect to MLCC or other electronic components. Experience of successful product development in the field of electronic components is beneficial.
Education/Experience:
B.S. in Engineering (Materials, Ceramic or Chemical) at minimum; M.S. or Ph.D. in Engineering or Science is strongly preferred. Minimum 5 years of applicable experience.
Years of experience:
5 or more
Computer Skills:
Proficiency in using Windows PC and Microsoft Office suite, in particular: Word, Excel, PowerPoint, Microsoft-Project and statistical analysis software such as MiniTab
3) Software Development Manager II (Pleasanton, CA)
My exciting Biotech Client uses nanoliter-sized droplets as reaction vessels to power a super-precise digital nucleic acid measurement method (droplet digital PCR). Now that they’ve solidified their market lead in digital PCR, they are expanding into diagnostic applications for core technology. A lot of interesting molecular biology can be done with thousands of nanoliter-sized reactors.
They need a creative software engineering manager with strong interpersonal skills to lead a dynamic software team building the next generation ddPCR applications. Major product functions include instrument control, data collection, visualization and analysis. You will work closely with MEs, EEs, ChEs & chemists, fluidics engineers, and molecular biologists.
About you:
· You have a technical background and are able to contribute to planning and design discussions. In addition to .NET/C#, you have some experience in Python, C++ or Java.
· You have experience leading a team and guiding them in their career development.
· You believe in building both teams and products that are responsive and high quality.
· You can motivate and instill a strong sense of ownership in your team.
· You have experience guiding teams through planning, prioritization, and execution of work using the Scrum framework. You are steadfastly focused on your customers.
· You are comfortable engaging in a back-and-forth with scientists, marketing, and regulatory personnel to figure out what we really need to provide.
· You enjoy sharing your expertise. You make everyone around you better. You like working as part of a team. You think ahead and build for the future.
· 10 years experience in SW development with at least 5 years as a manager designing and developing desktop apps in .NET/C# for life science or medical capital equipment.
· Experience developing regulated products for FDA, CLIA, CFR11/21, CE/IVD and cFDA.
· You have at least a BS in a relevant field, MS preferred.
· Solid understanding of and demonstrated experience using agile project management tools such as Jira/Greenhopper, Rally, VersionOne or equivalent. You believe in TDD.
· Experience with continuous integration/automated test tools such as Jenkins or TeamCity, and configuration/provisioning & deployment management: Puppet, Ansible
If you are interested in any of these outstanding opportunities, please send me a resume. Random resume submissions are always welcome, too. Referrals and recommendations are greatly appreciated.
Merely receiving this written material does not constitute or imply a "job offer", but is primarily a networking and informational tool for interested recipients.
Best Regards,
Nicholas Meyler
GM/President, Technology
Wingate Dunross, Inc.
ph (818)597-3200 ext. 211
<nickm(a)wdsearch.com>
Article by Doug Peckover, Inventor of "Tokenization" Security: <https://www.linkedin.com/pulse/privacy-vs-security-you-ready-nicholas-mey...>
http://app.streamsend.com/private/u4Kt/nKR/rPOzpjo/unsubscribe/28026195
5 years, 6 months
[GIT PULL] libnvdimm fixes for 4.9-final
by Williams, Dan J
Hi Linus, please pull from:
git://git.kernel.org/pub/scm/linux/kernel/git/nvdimm/nvdimm libnvdimm-fixes
...to receive several fixes to the DSM (ACPI device specific method)
marshaling implementation.
I consider these urgent enough to send for 4.9 consideration since they
fix the kernel's handling of ARS (Address Range Scrub) commands.
Especially for platforms without machine-check-recovery capabilities,
successful execution of ARS commands enables the platform to
potentially break out of an infinite reboot problem if a media error is
present in the boot path. There is also a one line fix for a device-dax
read-only mapping regression.
"acpi, nfit: fix extended status translations for ACPI DSMs" and
"device-dax: fix private mapping restriction, permit read-only" are
true regression fixes for changes introduced this cycle. "acpi, nfit,
libnvdimm: fix / harden ars_status output length handling" fixes the
kernel's handling of zero-length results, this never would have worked
in the past, but we only just recently discovered a BIOS implementation
that emits this arguably spec non-compliant result. The remaining two
commits are additional fall out from thinking through the implications
of a zero / truncated length result of the ARS Status command.
In order to mitigate the risk that these changes introduce yet more
regressions they are backstopped by a new unit test in
"tools/testing/nvdimm: unit test acpi_nfit_ctl()" that mocks inputs to
acpi_nfit_ctl().
Please consider pulling for 4.9, it has appeared in a -next release
with no reported issues.
The following changes since commit 3e5de27e940d00d8d504dfb96625fb654f641509:
Linux 4.9-rc8 (2016-12-04 12:50:51 -0800)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/nvdimm/nvdimm libnvdimm-fixes
for you to fetch changes up to 325896ffdf90f7cbd59fb873b7ba20d60d1ddf3c:
device-dax: fix private mapping restriction, permit read-only (2016-12-06 17:42:37 -0800)
----------------------------------------------------------------
Dan Williams (5):
acpi, nfit, libnvdimm: fix / harden ars_status output length handling
acpi, nfit: validate ars_status output buffer size
acpi, nfit: fix bus vs dimm confusion in xlat_status
tools/testing/nvdimm: unit test acpi_nfit_ctl()
device-dax: fix private mapping restriction, permit read-only
Vishal Verma (1):
acpi, nfit: fix extended status translations for ACPI DSMs
drivers/acpi/nfit/core.c | 55 +++++---
drivers/acpi/nfit/nfit.h | 2 +
drivers/dax/dax.c | 2 +-
drivers/nvdimm/bus.c | 25 +++-
include/linux/libnvdimm.h | 2 +-
tools/testing/nvdimm/Kbuild | 1 +
tools/testing/nvdimm/test/iomap.c | 23 +++-
tools/testing/nvdimm/test/nfit.c | 236 +++++++++++++++++++++++++++++++++-
tools/testing/nvdimm/test/nfit_test.h | 8 +-
9 files changed, 326 insertions(+), 28 deletions(-)
commit 9a901f5495e26e691c7d0ea7b6057a2f3e6330ed
Author: Vishal Verma <vishal.l.verma(a)intel.com>
Date: Mon Dec 5 17:00:37 2016 -0700
acpi, nfit: fix extended status translations for ACPI DSMs
ACPI DSMs can have an 'extended' status which can be non-zero to convey
additional information about the command. In the xlat_status routine,
where we translate the command statuses, we were returning an error for
a non-zero extended status, even if the primary status indicated success.
Return from each command's 'case' once we have verified both its status
and extend status are good.
Cc: <stable(a)vger.kernel.org>
Fixes: 11294d63ac91 ("nfit: fail DSMs that return non-zero status by default")
Signed-off-by: Vishal Verma <vishal.l.verma(a)intel.com>
Signed-off-by: Dan Williams <dan.j.williams(a)intel.com>
commit efda1b5d87cbc3d8816f94a3815b413f1868e10d
Author: Dan Williams <dan.j.williams(a)intel.com>
Date: Tue Dec 6 09:10:12 2016 -0800
acpi, nfit, libnvdimm: fix / harden ars_status output length handling
Given ambiguities in the ACPI 6.1 definition of the "Output (Size)"
field of the ARS (Address Range Scrub) Status command, a firmware
implementation may in practice return 0, 4, or 8 to indicate that there
is no output payload to process.
The specification states "Size of Output Buffer in bytes, including this
field.". However, 'Output Buffer' is also the name of the entire
payload, and earlier in the specification it states "Max Query ARS
Status Output Buffer Size: Maximum size of buffer (including the Status
and Extended Status fields)".
Without this fix if the BIOS happens to return 0 it causes memory
corruption as evidenced by this result from the acpi_nfit_ctl() unit
test.
ars_status00000000: 00020000 00000000 ........
BUG: stack guard page was hit at ffffc90001750000 (stack is ffffc9000174c000..ffffc9000174ffff)
kernel stack overflow (page fault): 0000 [#1] SMP DEBUG_PAGEALLOC
task: ffff8803332d2ec0 task.stack: ffffc9000174c000
RIP: 0010:[<ffffffff814cfe72>] [<ffffffff814cfe72>] __memcpy+0x12/0x20
RSP: 0018:ffffc9000174f9a8 EFLAGS: 00010246
RAX: ffffc9000174fab8 RBX: 0000000000000000 RCX: 000000001fffff56
RDX: 0000000000000000 RSI: ffff8803231f5a08 RDI: ffffc90001750000
RBP: ffffc9000174fa88 R08: ffffc9000174fab0 R09: ffff8803231f54b8
R10: 0000000000000008 R11: 0000000000000001 R12: 0000000000000000
R13: 0000000000000000 R14: 0000000000000003 R15: ffff8803231f54a0
FS: 00007f3a611af640(0000) GS:ffff88033ed00000(0000) knlGS:0000000000000000
CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033
CR2: ffffc90001750000 CR3: 0000000325b20000 CR4: 00000000000406e0
Stack:
ffffffffa00bc60d 0000000000000008 ffffc90000000001 ffffc9000174faac
0000000000000292 ffffffffa00c24e4 ffffffffa00c2914 0000000000000000
0000000000000000 ffffffff00000003 ffff880331ae8ad0 0000000800000246
Call Trace:
[<ffffffffa00bc60d>] ? acpi_nfit_ctl+0x49d/0x750 [nfit]
[<ffffffffa01f4fe0>] nfit_test_probe+0x670/0xb1b [nfit_test]
Cc: <stable(a)vger.kernel.org>
Fixes: 747ffe11b440 ("libnvdimm, tools/testing/nvdimm: fix 'ars_status' output buffer sizing")
Signed-off-by: Dan Williams <dan.j.williams(a)intel.com>
commit 82aa37cf09867c5e2c0326649d570e5b25c1189a
Author: Dan Williams <dan.j.williams(a)intel.com>
Date: Tue Dec 6 12:45:24 2016 -0800
acpi, nfit: validate ars_status output buffer size
If an ARS Status command returns truncated output, do not process
partial records or otherwise consume non-status fields.
Cc: <stable(a)vger.kernel.org>
Fixes: 0caeef63e6d2 ("libnvdimm: Add a poison list and export badblocks")
Signed-off-by: Dan Williams <dan.j.williams(a)intel.com>
commit d6eb270c57fef35798525004ddf2ac5dcdadd43b
Author: Dan Williams <dan.j.williams(a)intel.com>
Date: Tue Dec 6 15:06:55 2016 -0800
acpi, nfit: fix bus vs dimm confusion in xlat_status
Given dimms and bus commands share the same command number space we need
to be careful that we are translating status in the correct context.
Otherwise we can, for example, fail an ND_CMD_GET_CONFIG_SIZE command
because max_xfer is zero. It fails because that condition erroneously
correlates with the 'cleared == 0' failure of ND_CMD_CLEAR_ERROR.
Cc: <stable(a)vger.kernel.org>
Fixes: aef253382266 ("libnvdimm, nfit: centralize command status translation")
Signed-off-by: Dan Williams <dan.j.williams(a)intel.com>
commit a7de92dac9f0dbf01deb56fe1d661d7baac097e1
Author: Dan Williams <dan.j.williams(a)intel.com>
Date: Mon Dec 5 13:43:25 2016 -0800
tools/testing/nvdimm: unit test acpi_nfit_ctl()
A recent flurry of bug discoveries in the nfit driver's DSM marshalling
routine has highlighted the fact that we do not have unit test coverage
for this routine. Add a self-test of acpi_nfit_ctl() routine before
probing the "nfit_test.0" device. This mocks stimulus to acpi_nfit_ctl()
and if any of the tests fail "nfit_test.0" will be unavailable causing
the rest of the tests to not run / fail.
This unit test will also be a place to land reproductions of quirky BIOS
behavior discovered in the field and ensure the kernel does not regress
against implementations it has seen in practice.
Signed-off-by: Dan Williams <dan.j.williams(a)intel.com>
commit 325896ffdf90f7cbd59fb873b7ba20d60d1ddf3c
Author: Dan Williams <dan.j.williams(a)intel.com>
Date: Tue Dec 6 17:03:35 2016 -0800
device-dax: fix private mapping restriction, permit read-only
Hugh notes in response to commit 4cb19355ea19 "device-dax: fail all
private mapping attempts":
"I think that is more restrictive than you intended: haven't tried, but I
believe it rejects a PROT_READ, MAP_SHARED, O_RDONLY fd mmap, leaving no
way to mmap /dev/dax without write permission to it."
Indeed it does restrict read-only mappings, switch to checking
VM_MAYSHARE, not VM_SHARED.
Cc: <stable(a)vger.kernel.org>
Cc: Dave Hansen <dave.hansen(a)linux.intel.com>
Cc: Pawel Lebioda <pawel.lebioda(a)intel.com>
Fixes: 4cb19355ea19 ("device-dax: fail all private mapping attempts")
Reported-by: Hugh Dickins <hughd(a)google.com>
Signed-off-by: Dan Williams <dan.j.williams(a)intel.com>
5 years, 6 months
[PATCH 0/6 v2] dax: Page invalidation fixes
by Jan Kara
Hello,
this is second revision of my fixes of races when invalidating hole pages in
DAX mappings. See changelogs for details. The series is based on my patches to
write-protect DAX PTEs which are currently carried in mm tree. This is a hard
dependency because we really need to closely track dirtiness (and cleanness!)
of radix tree entries in DAX mappings in order to avoid discarding valid dirty
bits leading to missed cache flushes on fsync(2).
The tests have passed xfstests for xfs and ext4 in DAX and non-DAX mode.
I'd like to get some review of the patches (MM/FS people, please check whether
you like the direction changes in mm/truncate.c take in patch 2/6 - added
Johannes to CC since he was touching related code recently) so that these
patches can land in some tree once DAX write-protection patches are merged.
I'm hoping to get at least first three patches merged for 4.10-rc2... Thanks!
Changes since v1:
* Rebased on top of patches in mm tree
* Added some Reviewed-by tags
* renamed some functions based on review feedback
Honza
5 years, 6 months
Re: [PATCH 08/11] ACPICA: Tables: Back port acpi_get_table_with_size() and early_acpi_os_unmap_memory() from Linux kernel
by Dan Williams
On Tue, Nov 29, 2016 at 11:21 PM, Lv Zheng <lv.zheng(a)intel.com> wrote:
> ACPICA commit cac6790954d4d752a083e6122220b8a22febcd07
>
> This patch back ports Linux acpi_get_table_with_size() and
> early_acpi_os_unmap_memory() into ACPICA upstream to reduce divergences.
>
> The 2 APIs are used by Linux as table management APIs for long time, it
> contains a hidden logic that during the early stage, the mapped tables
> should be unmapped before the early stage ends.
>
> During the early stage, tables are handled by the following sequence:
> acpi_get_table_with_size();
> parse the table
> early_acpi_os_unmap_memory();
> During the late stage, tables are handled by the following sequence:
> acpi_get_table();
> parse the table
> Linux uses acpi_gbl_permanent_mmap to distinguish the early stage and the
> late stage.
>
> The reasoning of introducing acpi_get_table_with_size() is: ACPICA will
> remember the early mapped pointer in acpi_get_table() and Linux isn't able to
> prevent ACPICA from using the wrong early mapped pointer during the late
> stage as there is no API provided from ACPICA to be an inverse of
> acpi_get_table() to forget the early mapped pointer.
>
> But how ACPICA can work with the early/late stage requirement? Inside of
> ACPICA, tables are ensured to be remained in "INSTALLED" state during the
> early stage, and they are carefully not transitioned to "VALIDATED" state
> until the late stage. So the same logic is in fact implemented inside of
> ACPICA in a different way. The gap is only that the feature is not provided
> to the OSPMs in an accessible external API style.
>
> It then is possible to fix the gap by providing an inverse of
> acpi_get_table() from ACPICA, so that the two Linux sequences can be
> combined:
> acpi_get_table();
> parse the table
> acpi_put_table();
> In order to work easier with the current Linux code, acpi_get_table() and
> acpi_put_table() is implemented in a usage counting based style:
> 1. When the usage count of the table is increased from 0 to 1, table is
> mapped and .Pointer is set with the mapping address (VALIDATED);
> 2. When the usage count of the table is decreased from 1 to 0, .Pointer
> is unset and the mapping address is unmapped (INVALIDATED).
> So that we can deploy the new APIs to Linux with minimal effort by just
> invoking acpi_get_table() in acpi_get_table_with_size() and invoking
> acpi_put_table() in early_acpi_os_unmap_memory(). Lv Zheng.
>
> Link: https://github.com/acpica/acpica/commit/cac67909
> Signed-off-by: Lv Zheng <lv.zheng(a)intel.com>
> Signed-off-by: Bob Moore <robert.moore(a)intel.com>
This commit in -next (071b39575679 ACPICA: Tables: Back port
acpi_get_table_with_size() and early_acpi_os_unmap_memory() from Linux
kernel) causes a regression in my nfit/nvdimm test environment. The
nfit produced by QEMU no longer results in a nvdimm bus being created.
I have not root caused it, but I'm using the following command line
options to create an nfit in qemu-2.6. Reverting the commit leads
compile failures.
qemu=$HOME/git/qemu/build/x86_64-softmmu/qemu-system-x86_64
mem=$HOME/mem
label_size=$((128*1024))
mem_size=$(((3*1024*1024*1024) + (64 * 1024 *1024)))
IMAGE=$HOME/ahci.img
kvm=(
$qemu
-enable-kvm
-cpu kvm64
-kernel $kernel
-initrd $initrd
-m 12G,slots=3,maxmem=40G
-machine pc-i440fx-2.4,accel=kvm,usb=off,vmport=off,nvdimm
-cpu SandyBridge
-smp 2
-netdev tap,id=hostnet0,ifname=tap0,script=no,downscript=no
-device
virtio-net-pci,netdev=hostnet0,id=net0,mac=52:54:00:b7:a1:ad,bus=pci.0,addr=0x7
-object
memory-backend-file,id=mem1,share,mem-path=${mem},size=$((label_size +
mem_size))
-device nvdimm,memdev=mem1,id=nv1,label-size=${label_size}
-device ahci,id=sata0,bus=pci.0,addr=0x8
-drive file=$IMAGE,if=none,id=drive-sata0-0-0,format=raw
-device ide-hd,bus=sata0.0,drive=drive-sata0-0-0,id=sata0-0-0
-boot order=nc
-no-reboot
-watchdog i6300esb
-rtc base=localtime
-serial stdio
-display none
-monitor null
)
5 years, 6 months
[PATCH 2 1/2] ndctl: introduce 4k allocation support for creating namespace
by Dave Jiang
Existing implementation defaults all pages allocated as 2M superpages.
For nfit_test dax device we need 4k pages allocated to work properly.
Adding an --align,-a option to provide the alignment. Will accept
4k and 2M at the moment as proper parameter. No -a option still defaults
to 2M.
Signed-off-by: Dave Jiang <dave.jiang(a)intel.com>
---
ndctl/builtin-xaction-namespace.c | 34 +++++++++++++++++++++++++++++++---
util/size.h | 1 +
2 files changed, 32 insertions(+), 3 deletions(-)
diff --git a/ndctl/builtin-xaction-namespace.c b/ndctl/builtin-xaction-namespace.c
index 8257eb9..038e59f 100644
--- a/ndctl/builtin-xaction-namespace.c
+++ b/ndctl/builtin-xaction-namespace.c
@@ -49,6 +49,7 @@ static struct parameters {
const char *region;
const char *reconfig;
const char *sector_size;
+ const char *align;
} param;
void builtin_xaction_namespace_reset(void)
@@ -71,6 +72,7 @@ struct parsed_parameters {
enum ndctl_namespace_mode mode;
unsigned long long size;
unsigned long sector_size;
+ unsigned long align;
};
#define debug(fmt, ...) \
@@ -104,6 +106,8 @@ OPT_STRING('l', "sector-size", ¶m.sector_size, "lba-size", \
"specify the logical sector size in bytes"), \
OPT_STRING('t', "type", ¶m.type, "type", \
"specify the type of namespace to create 'pmem' or 'blk'"), \
+OPT_STRING('a', "align", ¶m.align, "align", \
+ "specify the namespace alignment in bytes (default: 0x200000 (2M))"), \
OPT_BOOLEAN('f', "force", &force, "reconfigure namespace even if currently active")
static const struct option base_options[] = {
@@ -319,14 +323,13 @@ static int setup_namespace(struct ndctl_region *region,
try(ndctl_pfn, set_uuid, pfn, uuid);
try(ndctl_pfn, set_location, pfn, p->loc);
-
/*
* TODO: when we allow setting a non-default alignment
* we'll need to check for "has_align" earlier and fail
* non-default attempts on older kernels.
*/
if (ndctl_pfn_has_align(pfn))
- try(ndctl_pfn, set_align, pfn, SZ_2M);
+ try(ndctl_pfn, set_align, pfn, p->align);
try(ndctl_pfn, set_namespace, pfn, ndns);
rc = ndctl_pfn_enable(pfn);
} else if (p->mode == NDCTL_NS_MODE_DAX) {
@@ -335,7 +338,7 @@ static int setup_namespace(struct ndctl_region *region,
try(ndctl_dax, set_uuid, dax, uuid);
try(ndctl_dax, set_location, dax, p->loc);
/* device-dax assumes 'align' attribute present */
- try(ndctl_dax, set_align, dax, SZ_2M);
+ try(ndctl_dax, set_align, dax, p->align);
try(ndctl_dax, set_namespace, dax, ndns);
rc = ndctl_dax_enable(dax);
} else if (p->mode == NDCTL_NS_MODE_SAFE) {
@@ -439,6 +442,31 @@ static int validate_namespace_options(struct ndctl_region *region,
} else if (ndns)
p->mode = ndctl_namespace_get_mode(ndns);
+ if ((p->mode == NDCTL_NS_MODE_MEMORY) ||
+ (p->mode == NDCTL_NS_MODE_DAX)) {
+ struct ndctl_pfn *pfn = ndctl_region_get_pfn_seed(region);
+
+ if (!ndctl_pfn_has_align(pfn))
+ return -EINVAL;
+
+ if (param.align) {
+ p->align = parse_size64(param.align);
+ switch (p->align) {
+ case SZ_4K:
+ case SZ_2M:
+ break;
+ case SZ_1G: /* unsupported yet... */
+ default:
+ debug("%s: invalid align\n", __func__);
+ return -EINVAL;
+ }
+ } else
+ p->align = SZ_2M;
+ } else if (param.align) {
+ debug("%s: does not support align\n", __func__);
+ return -EINVAL;
+ }
+
if (param.sector_size) {
struct ndctl_btt *btt;
int num, i;
diff --git a/util/size.h b/util/size.h
index 50917a5..634c926 100644
--- a/util/size.h
+++ b/util/size.h
@@ -2,6 +2,7 @@
#define _NDCTL_SIZE_H_
#define SZ_1K 0x00000400
+#define SZ_4K 0x00001000
#define SZ_1M 0x00100000
#define SZ_2M 0x00200000
#define SZ_4M 0x00400000
5 years, 6 months
