[linux-next:master 2534/4685] drivers/clk/clk-versaclock5.c:736 vc5_probe() warn: passing freed memory 'init.name'
1:47 p.m.
CC: kbuild-all(a)lists.01.org
TO: Adam Ford <aford173(a)gmail.com>
CC: Stephen Boyd <sboyd(a)kernel.org>
tree: https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
head: aab2003999e78bbf2058dae1e661c44ede1d9766
commit: f491276a5168598758ea7fc381195e4ba9af39f8 [2534/4685] clk: vc5: Allow Versaclock
driver to support multiple instances
:::::: branch date: 6 hours ago
:::::: commit date: 8 days ago
config: i386-randconfig-m021-20200701 (attached as .config)
compiler: gcc-9 (Debian 9.3.0-14) 9.3.0
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp(a)intel.com>
Reported-by: Dan Carpenter <dan.carpenter(a)oracle.com>
New smatch warnings:
drivers/clk/clk-versaclock5.c:736 vc5_probe() warn: passing freed memory
'init.name'
Old smatch warnings:
drivers/clk/clk-versaclock5.c:754 vc5_probe() warn: passing freed memory
'init.name'
drivers/clk/clk-versaclock5.c:775 vc5_probe() warn: passing freed memory
'init.name'
drivers/clk/clk-versaclock5.c:793 vc5_probe() warn: passing freed memory
'init.name'
drivers/clk/clk-versaclock5.c:814 vc5_probe() warn: passing freed memory
'init.name'
drivers/clk/clk-versaclock5.c:835 vc5_probe() warn: passing freed memory
'init.name'
drivers/clk/clk-versaclock5.c:862 vc5_probe() warn: passing freed memory
'init.name'
#
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commi...
git remote add linux-next
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git
git remote update linux-next
git checkout f491276a5168598758ea7fc381195e4ba9af39f8
vim +736 drivers/clk/clk-versaclock5.c
3e1aec4e2c4153 Marek Vasut 2017-01-12 670
f491276a516859 Adam Ford 2020-06-03 671 static int vc5_probe(struct i2c_client
*client, const struct i2c_device_id *id)
3e1aec4e2c4153 Marek Vasut 2017-01-12 672 {
3e1aec4e2c4153 Marek Vasut 2017-01-12 673 struct vc5_driver_data *vc5;
3e1aec4e2c4153 Marek Vasut 2017-01-12 674 struct clk_init_data init;
3e1aec4e2c4153 Marek Vasut 2017-01-12 675 const char *parent_names[2];
9adddb01ce5f71 Alexey Firago 2017-04-07 676 unsigned int n, idx = 0;
3e1aec4e2c4153 Marek Vasut 2017-01-12 677 int ret;
3e1aec4e2c4153 Marek Vasut 2017-01-12 678
3e1aec4e2c4153 Marek Vasut 2017-01-12 679 vc5 = devm_kzalloc(&client->dev,
sizeof(*vc5), GFP_KERNEL);
3e1aec4e2c4153 Marek Vasut 2017-01-12 680 if (vc5 == NULL)
3e1aec4e2c4153 Marek Vasut 2017-01-12 681 return -ENOMEM;
3e1aec4e2c4153 Marek Vasut 2017-01-12 682
3e1aec4e2c4153 Marek Vasut 2017-01-12 683 i2c_set_clientdata(client, vc5);
3e1aec4e2c4153 Marek Vasut 2017-01-12 684 vc5->client = client;
9adddb01ce5f71 Alexey Firago 2017-04-07 685 vc5->chip_info =
of_device_get_match_data(&client->dev);
3e1aec4e2c4153 Marek Vasut 2017-01-12 686
3e1aec4e2c4153 Marek Vasut 2017-01-12 687 vc5->pin_xin =
devm_clk_get(&client->dev, "xin");
3e1aec4e2c4153 Marek Vasut 2017-01-12 688 if (PTR_ERR(vc5->pin_xin) ==
-EPROBE_DEFER)
3e1aec4e2c4153 Marek Vasut 2017-01-12 689 return -EPROBE_DEFER;
3e1aec4e2c4153 Marek Vasut 2017-01-12 690
3e1aec4e2c4153 Marek Vasut 2017-01-12 691 vc5->pin_clkin =
devm_clk_get(&client->dev, "clkin");
3e1aec4e2c4153 Marek Vasut 2017-01-12 692 if (PTR_ERR(vc5->pin_clkin) ==
-EPROBE_DEFER)
3e1aec4e2c4153 Marek Vasut 2017-01-12 693 return -EPROBE_DEFER;
3e1aec4e2c4153 Marek Vasut 2017-01-12 694
3e1aec4e2c4153 Marek Vasut 2017-01-12 695 vc5->regmap =
devm_regmap_init_i2c(client, &vc5_regmap_config);
3e1aec4e2c4153 Marek Vasut 2017-01-12 696 if (IS_ERR(vc5->regmap)) {
3e1aec4e2c4153 Marek Vasut 2017-01-12 697 dev_err(&client->dev, "failed
to allocate register map\n");
3e1aec4e2c4153 Marek Vasut 2017-01-12 698 return PTR_ERR(vc5->regmap);
3e1aec4e2c4153 Marek Vasut 2017-01-12 699 }
3e1aec4e2c4153 Marek Vasut 2017-01-12 700
3e1aec4e2c4153 Marek Vasut 2017-01-12 701 /* Register clock input mux */
3e1aec4e2c4153 Marek Vasut 2017-01-12 702 memset(&init, 0, sizeof(init));
3e1aec4e2c4153 Marek Vasut 2017-01-12 703
3e1aec4e2c4153 Marek Vasut 2017-01-12 704 if (!IS_ERR(vc5->pin_xin)) {
3e1aec4e2c4153 Marek Vasut 2017-01-12 705 vc5->clk_mux_ins |= VC5_MUX_IN_XIN;
3e1aec4e2c4153 Marek Vasut 2017-01-12 706 parent_names[init.num_parents++] =
__clk_get_name(vc5->pin_xin);
9adddb01ce5f71 Alexey Firago 2017-04-07 707 } else if (vc5->chip_info->flags
& VC5_HAS_INTERNAL_XTAL) {
3e1aec4e2c4153 Marek Vasut 2017-01-12 708 vc5->pin_xin =
clk_register_fixed_rate(&client->dev,
3e1aec4e2c4153 Marek Vasut 2017-01-12 709 "internal-xtal",
NULL,
3e1aec4e2c4153 Marek Vasut 2017-01-12 710 0, 25000000);
3e1aec4e2c4153 Marek Vasut 2017-01-12 711 if (IS_ERR(vc5->pin_xin))
3e1aec4e2c4153 Marek Vasut 2017-01-12 712 return PTR_ERR(vc5->pin_xin);
3e1aec4e2c4153 Marek Vasut 2017-01-12 713 vc5->clk_mux_ins |= VC5_MUX_IN_XIN;
3e1aec4e2c4153 Marek Vasut 2017-01-12 714 parent_names[init.num_parents++] =
__clk_get_name(vc5->pin_xin);
3e1aec4e2c4153 Marek Vasut 2017-01-12 715 }
3e1aec4e2c4153 Marek Vasut 2017-01-12 716
3e1aec4e2c4153 Marek Vasut 2017-01-12 717 if (!IS_ERR(vc5->pin_clkin)) {
3e1aec4e2c4153 Marek Vasut 2017-01-12 718 vc5->clk_mux_ins |= VC5_MUX_IN_CLKIN;
3e1aec4e2c4153 Marek Vasut 2017-01-12 719 parent_names[init.num_parents++] =
3e1aec4e2c4153 Marek Vasut 2017-01-12 720 __clk_get_name(vc5->pin_clkin);
3e1aec4e2c4153 Marek Vasut 2017-01-12 721 }
3e1aec4e2c4153 Marek Vasut 2017-01-12 722
3e1aec4e2c4153 Marek Vasut 2017-01-12 723 if (!init.num_parents) {
3e1aec4e2c4153 Marek Vasut 2017-01-12 724 dev_err(&client->dev, "no
input clock specified!\n");
3e1aec4e2c4153 Marek Vasut 2017-01-12 725 return -EINVAL;
3e1aec4e2c4153 Marek Vasut 2017-01-12 726 }
3e1aec4e2c4153 Marek Vasut 2017-01-12 727
f491276a516859 Adam Ford 2020-06-03 728 init.name = kasprintf(GFP_KERNEL,
"%pOFn.mux", client->dev.of_node);
3e1aec4e2c4153 Marek Vasut 2017-01-12 729 init.ops = &vc5_mux_ops;
3e1aec4e2c4153 Marek Vasut 2017-01-12 730 init.flags = 0;
3e1aec4e2c4153 Marek Vasut 2017-01-12 731 init.parent_names = parent_names;
3e1aec4e2c4153 Marek Vasut 2017-01-12 732 vc5->clk_mux.init = &init;
3e1aec4e2c4153 Marek Vasut 2017-01-12 733 ret =
devm_clk_hw_register(&client->dev, &vc5->clk_mux);
f491276a516859 Adam Ford 2020-06-03 734 kfree(init.name); /* clock framework made a
copy of the name */
3e1aec4e2c4153 Marek Vasut 2017-01-12 735 if (ret) {
3e1aec4e2c4153 Marek Vasut 2017-01-12 @736 dev_err(&client->dev, "unable
to register %s\n", init.name);
3e1aec4e2c4153 Marek Vasut 2017-01-12 737 goto err_clk;
3e1aec4e2c4153 Marek Vasut 2017-01-12 738 }
3e1aec4e2c4153 Marek Vasut 2017-01-12 739
8c1ebe97626701 Marek Vasut 2017-07-09 740 if (vc5->chip_info->flags &
VC5_HAS_PFD_FREQ_DBL) {
8c1ebe97626701 Marek Vasut 2017-07-09 741 /* Register frequency doubler */
8c1ebe97626701 Marek Vasut 2017-07-09 742 memset(&init, 0, sizeof(init));
f491276a516859 Adam Ford 2020-06-03 743 init.name = kasprintf(GFP_KERNEL,
"%pOFn.dbl",
f491276a516859 Adam Ford 2020-06-03 744 client->dev.of_node);
8c1ebe97626701 Marek Vasut 2017-07-09 745 init.ops = &vc5_dbl_ops;
8c1ebe97626701 Marek Vasut 2017-07-09 746 init.flags = CLK_SET_RATE_PARENT;
f491276a516859 Adam Ford 2020-06-03 747 init.parent_names = parent_names;
f491276a516859 Adam Ford 2020-06-03 748 parent_names[0] =
clk_hw_get_name(&vc5->clk_mux);
8c1ebe97626701 Marek Vasut 2017-07-09 749 init.num_parents = 1;
8c1ebe97626701 Marek Vasut 2017-07-09 750 vc5->clk_mul.init = &init;
8c1ebe97626701 Marek Vasut 2017-07-09 751 ret =
devm_clk_hw_register(&client->dev, &vc5->clk_mul);
f491276a516859 Adam Ford 2020-06-03 752 kfree(init.name); /* clock framework made
a copy of the name */
8c1ebe97626701 Marek Vasut 2017-07-09 753 if (ret) {
8c1ebe97626701 Marek Vasut 2017-07-09 754 dev_err(&client->dev, "unable
to register %s\n",
8c1ebe97626701 Marek Vasut 2017-07-09 755 init.name);
8c1ebe97626701 Marek Vasut 2017-07-09 756 goto err_clk;
8c1ebe97626701 Marek Vasut 2017-07-09 757 }
8c1ebe97626701 Marek Vasut 2017-07-09 758 }
8c1ebe97626701 Marek Vasut 2017-07-09 759
55997db52e997e Marek Vasut 2017-07-09 760 /* Register PFD */
55997db52e997e Marek Vasut 2017-07-09 761 memset(&init, 0, sizeof(init));
f491276a516859 Adam Ford 2020-06-03 762 init.name = kasprintf(GFP_KERNEL,
"%pOFn.pfd", client->dev.of_node);
55997db52e997e Marek Vasut 2017-07-09 763 init.ops = &vc5_pfd_ops;
55997db52e997e Marek Vasut 2017-07-09 764 init.flags = CLK_SET_RATE_PARENT;
f491276a516859 Adam Ford 2020-06-03 765 init.parent_names = parent_names;
8c1ebe97626701 Marek Vasut 2017-07-09 766 if (vc5->chip_info->flags &
VC5_HAS_PFD_FREQ_DBL)
f491276a516859 Adam Ford 2020-06-03 767 parent_names[0] =
clk_hw_get_name(&vc5->clk_mul);
8c1ebe97626701 Marek Vasut 2017-07-09 768 else
f491276a516859 Adam Ford 2020-06-03 769 parent_names[0] =
clk_hw_get_name(&vc5->clk_mux);
55997db52e997e Marek Vasut 2017-07-09 770 init.num_parents = 1;
55997db52e997e Marek Vasut 2017-07-09 771 vc5->clk_pfd.init = &init;
55997db52e997e Marek Vasut 2017-07-09 772 ret =
devm_clk_hw_register(&client->dev, &vc5->clk_pfd);
f491276a516859 Adam Ford 2020-06-03 773 kfree(init.name); /* clock framework made a
copy of the name */
55997db52e997e Marek Vasut 2017-07-09 774 if (ret) {
55997db52e997e Marek Vasut 2017-07-09 775 dev_err(&client->dev, "unable
to register %s\n", init.name);
55997db52e997e Marek Vasut 2017-07-09 776 goto err_clk;
55997db52e997e Marek Vasut 2017-07-09 777 }
55997db52e997e Marek Vasut 2017-07-09 778
3e1aec4e2c4153 Marek Vasut 2017-01-12 779 /* Register PLL */
3e1aec4e2c4153 Marek Vasut 2017-01-12 780 memset(&init, 0, sizeof(init));
f491276a516859 Adam Ford 2020-06-03 781 init.name = kasprintf(GFP_KERNEL,
"%pOFn.pll", client->dev.of_node);
3e1aec4e2c4153 Marek Vasut 2017-01-12 782 init.ops = &vc5_pll_ops;
3e1aec4e2c4153 Marek Vasut 2017-01-12 783 init.flags = CLK_SET_RATE_PARENT;
f491276a516859 Adam Ford 2020-06-03 784 init.parent_names = parent_names;
f491276a516859 Adam Ford 2020-06-03 785 parent_names[0] =
clk_hw_get_name(&vc5->clk_pfd);
3e1aec4e2c4153 Marek Vasut 2017-01-12 786 init.num_parents = 1;
3e1aec4e2c4153 Marek Vasut 2017-01-12 787 vc5->clk_pll.num = 0;
3e1aec4e2c4153 Marek Vasut 2017-01-12 788 vc5->clk_pll.vc5 = vc5;
3e1aec4e2c4153 Marek Vasut 2017-01-12 789 vc5->clk_pll.hw.init = &init;
3e1aec4e2c4153 Marek Vasut 2017-01-12 790 ret =
devm_clk_hw_register(&client->dev, &vc5->clk_pll.hw);
f491276a516859 Adam Ford 2020-06-03 791 kfree(init.name); /* clock framework made a
copy of the name */
3e1aec4e2c4153 Marek Vasut 2017-01-12 792 if (ret) {
3e1aec4e2c4153 Marek Vasut 2017-01-12 793 dev_err(&client->dev, "unable
to register %s\n", init.name);
3e1aec4e2c4153 Marek Vasut 2017-01-12 794 goto err_clk;
3e1aec4e2c4153 Marek Vasut 2017-01-12 795 }
3e1aec4e2c4153 Marek Vasut 2017-01-12 796
3e1aec4e2c4153 Marek Vasut 2017-01-12 797 /* Register FODs */
9adddb01ce5f71 Alexey Firago 2017-04-07 798 for (n = 0; n <
vc5->chip_info->clk_fod_cnt; n++) {
9adddb01ce5f71 Alexey Firago 2017-04-07 799 idx =
vc5_map_index_to_output(vc5->chip_info->model, n);
3e1aec4e2c4153 Marek Vasut 2017-01-12 800 memset(&init, 0, sizeof(init));
f491276a516859 Adam Ford 2020-06-03 801 init.name = kasprintf(GFP_KERNEL,
"%pOFn.fod%d",
f491276a516859 Adam Ford 2020-06-03 802 client->dev.of_node, idx);
3e1aec4e2c4153 Marek Vasut 2017-01-12 803 init.ops = &vc5_fod_ops;
3e1aec4e2c4153 Marek Vasut 2017-01-12 804 init.flags = CLK_SET_RATE_PARENT;
f491276a516859 Adam Ford 2020-06-03 805 init.parent_names = parent_names;
f491276a516859 Adam Ford 2020-06-03 806 parent_names[0] =
clk_hw_get_name(&vc5->clk_pll.hw);
3e1aec4e2c4153 Marek Vasut 2017-01-12 807 init.num_parents = 1;
3e1aec4e2c4153 Marek Vasut 2017-01-12 808 vc5->clk_fod[n].num = idx;
3e1aec4e2c4153 Marek Vasut 2017-01-12 809 vc5->clk_fod[n].vc5 = vc5;
3e1aec4e2c4153 Marek Vasut 2017-01-12 810 vc5->clk_fod[n].hw.init = &init;
3e1aec4e2c4153 Marek Vasut 2017-01-12 811 ret =
devm_clk_hw_register(&client->dev, &vc5->clk_fod[n].hw);
f491276a516859 Adam Ford 2020-06-03 812 kfree(init.name); /* clock framework made
a copy of the name */
3e1aec4e2c4153 Marek Vasut 2017-01-12 813 if (ret) {
3e1aec4e2c4153 Marek Vasut 2017-01-12 814 dev_err(&client->dev, "unable
to register %s\n",
3e1aec4e2c4153 Marek Vasut 2017-01-12 815 init.name);
3e1aec4e2c4153 Marek Vasut 2017-01-12 816 goto err_clk;
3e1aec4e2c4153 Marek Vasut 2017-01-12 817 }
3e1aec4e2c4153 Marek Vasut 2017-01-12 818 }
3e1aec4e2c4153 Marek Vasut 2017-01-12 819
3e1aec4e2c4153 Marek Vasut 2017-01-12 820 /* Register MUX-connected OUT0_I2C_SELB
output */
3e1aec4e2c4153 Marek Vasut 2017-01-12 821 memset(&init, 0, sizeof(init));
f491276a516859 Adam Ford 2020-06-03 822 init.name = kasprintf(GFP_KERNEL,
"%pOFn.out0_sel_i2cb",
f491276a516859 Adam Ford 2020-06-03 823 client->dev.of_node);
3e1aec4e2c4153 Marek Vasut 2017-01-12 824 init.ops = &vc5_clk_out_ops;
3e1aec4e2c4153 Marek Vasut 2017-01-12 825 init.flags = CLK_SET_RATE_PARENT;
f491276a516859 Adam Ford 2020-06-03 826 init.parent_names = parent_names;
f491276a516859 Adam Ford 2020-06-03 827 parent_names[0] =
clk_hw_get_name(&vc5->clk_mux);
3e1aec4e2c4153 Marek Vasut 2017-01-12 828 init.num_parents = 1;
3e1aec4e2c4153 Marek Vasut 2017-01-12 829 vc5->clk_out[0].num = idx;
3e1aec4e2c4153 Marek Vasut 2017-01-12 830 vc5->clk_out[0].vc5 = vc5;
3e1aec4e2c4153 Marek Vasut 2017-01-12 831 vc5->clk_out[0].hw.init = &init;
3e1aec4e2c4153 Marek Vasut 2017-01-12 832 ret =
devm_clk_hw_register(&client->dev, &vc5->clk_out[0].hw);
f491276a516859 Adam Ford 2020-06-03 833 kfree(init.name); /* clock framework made a
copy of the name */
3e1aec4e2c4153 Marek Vasut 2017-01-12 834 if (ret) {
f491276a516859 Adam Ford 2020-06-03 835 dev_err(&client->dev, "unable
to register %s\n", init.name);
3e1aec4e2c4153 Marek Vasut 2017-01-12 836 goto err_clk;
3e1aec4e2c4153 Marek Vasut 2017-01-12 837 }
3e1aec4e2c4153 Marek Vasut 2017-01-12 838
3e1aec4e2c4153 Marek Vasut 2017-01-12 839 /* Register FOD-connected OUTx outputs */
9adddb01ce5f71 Alexey Firago 2017-04-07 840 for (n = 1; n <
vc5->chip_info->clk_out_cnt; n++) {
9adddb01ce5f71 Alexey Firago 2017-04-07 841 idx =
vc5_map_index_to_output(vc5->chip_info->model, n - 1);
f491276a516859 Adam Ford 2020-06-03 842 parent_names[0] =
clk_hw_get_name(&vc5->clk_fod[idx].hw);
3e1aec4e2c4153 Marek Vasut 2017-01-12 843 if (n == 1)
f491276a516859 Adam Ford 2020-06-03 844 parent_names[1] =
clk_hw_get_name(&vc5->clk_mux);
3e1aec4e2c4153 Marek Vasut 2017-01-12 845 else
f491276a516859 Adam Ford 2020-06-03 846 parent_names[1] =
f491276a516859 Adam Ford 2020-06-03 847
clk_hw_get_name(&vc5->clk_out[n - 1].hw);
3e1aec4e2c4153 Marek Vasut 2017-01-12 848
3e1aec4e2c4153 Marek Vasut 2017-01-12 849 memset(&init, 0, sizeof(init));
f491276a516859 Adam Ford 2020-06-03 850 init.name = kasprintf(GFP_KERNEL,
"%pOFn.out%d",
f491276a516859 Adam Ford 2020-06-03 851 client->dev.of_node, idx + 1);
3e1aec4e2c4153 Marek Vasut 2017-01-12 852 init.ops = &vc5_clk_out_ops;
3e1aec4e2c4153 Marek Vasut 2017-01-12 853 init.flags = CLK_SET_RATE_PARENT;
3e1aec4e2c4153 Marek Vasut 2017-01-12 854 init.parent_names = parent_names;
3e1aec4e2c4153 Marek Vasut 2017-01-12 855 init.num_parents = 2;
3e1aec4e2c4153 Marek Vasut 2017-01-12 856 vc5->clk_out[n].num = idx;
3e1aec4e2c4153 Marek Vasut 2017-01-12 857 vc5->clk_out[n].vc5 = vc5;
3e1aec4e2c4153 Marek Vasut 2017-01-12 858 vc5->clk_out[n].hw.init = &init;
f491276a516859 Adam Ford 2020-06-03 859 ret =
devm_clk_hw_register(&client->dev, &vc5->clk_out[n].hw);
f491276a516859 Adam Ford 2020-06-03 860 kfree(init.name); /* clock framework made
a copy of the name */
3e1aec4e2c4153 Marek Vasut 2017-01-12 861 if (ret) {
3e1aec4e2c4153 Marek Vasut 2017-01-12 862 dev_err(&client->dev, "unable
to register %s\n",
3e1aec4e2c4153 Marek Vasut 2017-01-12 863 init.name);
3e1aec4e2c4153 Marek Vasut 2017-01-12 864 goto err_clk;
3e1aec4e2c4153 Marek Vasut 2017-01-12 865 }
3e1aec4e2c4153 Marek Vasut 2017-01-12 866 }
3e1aec4e2c4153 Marek Vasut 2017-01-12 867
3e1aec4e2c4153 Marek Vasut 2017-01-12 868 ret =
of_clk_add_hw_provider(client->dev.of_node, vc5_of_clk_get, vc5);
3e1aec4e2c4153 Marek Vasut 2017-01-12 869 if (ret) {
3e1aec4e2c4153 Marek Vasut 2017-01-12 870 dev_err(&client->dev, "unable
to add clk provider\n");
3e1aec4e2c4153 Marek Vasut 2017-01-12 871 goto err_clk;
3e1aec4e2c4153 Marek Vasut 2017-01-12 872 }
3e1aec4e2c4153 Marek Vasut 2017-01-12 873
3e1aec4e2c4153 Marek Vasut 2017-01-12 874 return 0;
3e1aec4e2c4153 Marek Vasut 2017-01-12 875
3e1aec4e2c4153 Marek Vasut 2017-01-12 876 err_clk:
9adddb01ce5f71 Alexey Firago 2017-04-07 877 if (vc5->chip_info->flags &
VC5_HAS_INTERNAL_XTAL)
3e1aec4e2c4153 Marek Vasut 2017-01-12 878
clk_unregister_fixed_rate(vc5->pin_xin);
3e1aec4e2c4153 Marek Vasut 2017-01-12 879 return ret;
3e1aec4e2c4153 Marek Vasut 2017-01-12 880 }
3e1aec4e2c4153 Marek Vasut 2017-01-12 881
:::::: The code at line 736 was first introduced by commit
:::::: 3e1aec4e2c415346df7d5429f7413837ddaaedd7 clk: vc5: Add support for IDT VersaClock
5P49V5923 and 5P49V5933
:::::: TO: Marek Vasut <marek.vasut(a)gmail.com>
:::::: CC: Stephen Boyd <sboyd(a)codeaurora.org>
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0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
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